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« on: May 28, 2012, 06:13:58 am »
Another vhdl-related question, well circuit design-related. I am having some issues with optimization.
Lets say I start with a circuit with two flip flops and x amount of gates. Let's call the flip flops Q1 and Q0. I set up a gray coded state transition table with Q1Q0, Q1+ Q0+, input and output, to study how and when states change. I then put up two karnaugh tables, one for Q1+ and Q0+ to see exactly how the next states are decided.
What I am having problems understanding is how these two karnaugh tables interact to form the final optimized grid. As in how do I go from the karnaugh table back to a state transition table?
EDIT: I have a specific example btw if I make more sense with one.
I start with a circuit made up of two flip flops (Q1 and Q0), three gates, one output (out) and one input (in). The next Q1 is decided by ((Q1 or Q0) and in). The next Q0 is decided by (notQ1 and notQ0 and in).
Out <= Q1
Whenever the input is 0, th next state is Q1Q0 = 00
When input is 1:
Q1Q0 -> next
00 -> 01
01 -> 10
11 -> 10
10 -> 10
I notice that both the next state and the output are identical for 11 and 10 so I eliminate the 10 state and reroute 01 to 11 instead. I set up the karnaugh tables for Q1+ and Q0+ and perform optimization using the dont cares I got from removing a state.
What I end up with is:
Next Q1 = (Q0 and in)
Next Q0 = (NotQ1 and in)
Which brings me down to just two and gates. The issue lies in that I should supposedly only require one gate total and I just can't seem to wrap my head around it, I am obviously doing something wrong in either the state or karnaugh tables.
EDITEDIT: Oh shit I am stupid sometimes. I just realised I forgot to reroute the 11 state to 11 as well for input 1. Which means I can perform a bigger optimization in the karnaugh table for Q0 meaning in the end the next Q0 is only dependant on the input meaning I just need one and-gate for the Q1 state.
Sooo.. disregard this post I guess, just me being stupid again.