Dwarf Fortress > DF Dwarf Mode Discussion
Pre-Triggered Mechanical Logic
jjdorf:
I have been hard at work (in a lazy sort of way), designing a new "ideology" for mechanical logic. Inspired by Jong's Computer (here), and with a slight refinement to one of my gates by Dorf3000 (Thanks!), The result is, I believe, a very elegant, and more importantly, water conserving logic system. It can often use a minimum of power as well, and can be easier to build than the equivalent fluid logic gates; generally fewer mechanisms, less linking, few extra parts such as bridges, floodgates, etc., allowing more of the system to be built by dedicated mechanics dwarves, and only requiring a minimum of other construction labors. The full Wiki page I am using as a scratchpad for my ideas is here.
The first design ideology to consider is the following: All input signals to a gear are linked to the gear in logical true value. This means any levers linked should be flipped on by default. It also means that pressure plates from hybrid mechano-fluid gates are designed to be active on 0-3 water.
The second design ideology is that certain gears are pre-toggled in order to change the semantics of their logic. This is the key to not requiring any excess power load, such as used by these logic gates. A gear is pre-toggled by constructing a lever, linking it to the gear, flipping the lever, then dismantling the lever. A pre-toggled gear costs two mechanisms to build (not counting input links).
The third design ideology is that power is truly used as just power, and there are no requirements for calculating how much power the system will need, except for knowing the maximum power draw in a circuit. No basic mechanical logical gate draws more than 10 power for the functional parts, though power train not linked to a lever or pressure plate may draw more.
At this point, only two basic fluid using gates are part of this ideology. The first, which is commonly called a rotation sensor, I call a Fluid Logic Buffer (FL Buffer). It's purpose is simple: take an incoming signal from the result of a mechanical power train, including logical gates, and convert that into a signal from a pressure plate. This outgoing signal increases the "fan-out" of the signal, by being capable of linking to very many other gears.
The second fluid using gate is a Memory cell, designed as a D-Type flip flop. What this means is fairly simple. When the cells has power, it's pressure plate takes on the same signal as the incoming signal, the Data signal. If the data signal changes while the cell has power, the cell will change. Since a pressure plate is used, there is a latency of 100 steps when the data signal drops to zero. While the power is off, the cell retains the same value as the last Data value while it was on. Further changes at this time to the data signal will not cause the cell to change.
Details on these gates and the design can be found at my wiki page
Now, however, comes the more interesting part (IMHO). The mechanical logic gates. Some will be familiar, others will be new to some of you. Conventions used in gate diagrams: Power gear or train is identified with P. Output gear or train is identified with O. Input signals are I, A, B, i, a, or b. An input signal that is lower case must be pre-triggered.
ML Buffer
This is a mechanical buffer. It takes an incoming signal (Such as from an FL Buffer), a power supply, and outputs power - 5 if the signal is on.
--- Code: ---PIO
--- End code ---
Minus the input link, this costs only one mechanism and draws 5 power.
ML Inverter (NOT)
This is much like the buffer, except the signal is inverted. This is done by pre-toggling the input gear.
--- Code: ---PiO
--- End code ---
Minus the input link, this costs only two mechanisms and draws 5 power.
ML AND Gate
This is the same standard gate as most will be used to. No pre-toggled gears in this one. It has two input gears, A and B.
--- Code: ---PABO
--- End code ---
Minus the input links, this costs only two mechanisms and draws 10 power.
ML OR Gate
Another of the gates most will be used to seeing. I generally intend to build these vertically on two floors.
--- Code: ---PA
BO
--- End code ---
Minus the input links, this costs only two mechanisms and draws a maximum of 10 power.
ML NOR Gate
This is where the pre-toggling makes things more interesting. Due to the nature of logic gates, inverting the inputs to an AND gate results in a NOR gate. This is done by pre-toggling the inputs.
--- Code: ---PabO
--- End code ---
Minus the input links, this costs four mechanisms and draws 10 power.
ML NAND Gate
Like the NOR gate, inverting an OR gate's inputs results in a NAND gate, logically speaking. Again, this is done with pre-toggling.
--- Code: ---Pa
bO
--- End code ---
Minus the input links, this costs four mechanisms and draws a maximum of 10 power.
ML XOR Gate
This gate is deceptively simply, yet quite powerful. It combines two inputs onto a single gear, which is pre-toggled. When both inputs are on, or both are off, the gear will be disengaged. Only when one of the two inputs is on will the gear engage. This results in an extremely elegant XOR gate. I cannot take credit for this one. Thanks, Dorf3000!
--- Code: ---PiO
--- End code ---
Again: Both inputs are linked to the single gear (i).
Minus the input links, this costs two mechanisms and draws 5 power.
I am continuing some research, looking for ways to further my withdrawal from society... I may have taken on a secretive mood. Or perhaps a fey mood, considering I'm not being particularly secretive (though I am drawing lots of sketches, so to speak). Has the title of first computer design in DF2010 been claimed yet?
DarthCloakedDwarf:
Um...
Er...
I'm sure that post would be profound... if only I could understand the tiniest part of it.
Daenyth:
I eagerly await updates on this...
DarthCloakedDwarf:
--- Quote from: Daenyth on April 23, 2010, 10:35:09 pm ---I eagerly await updates on this...
--- End quote ---
In laymen's terms, preferably.
furrot:
I still don't think I'm crazy enough to play this game properly.
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