It's at least possible in theory, but I can't imagine that it would be possible to do in anything approaching a reasonable amount of time or effort. As Putnam has discovered, even multithreading parts of the game that are amenable to it has been difficult and not always worth doing. Offloading parts to dedicated hardware would be an order of magnitude harder, even with tools that try to do things like convert C code to Verilog or VHDL.
I'm pretty sure centralized memory access would always be the bottleneck in a system like that. As an example, Putnam mentioned that looking up familial relationships was a surprisingly big time sink in the game right now. That's almost certainly because of random memory accesses across GB of RAM. An accelerator board would mean the game has to pause at that step, shuttle the data over to the accelerator, let it do its job, shuttle the data back and then pick up where it left off. Isolating those bits of the historical figure data so only that has to be copied would help, but it's still a problem and adds complexities of its own.
I guess if you had a truly amazing FPGA with a modern x86 CPU attached that shared a memory bus, you might be able to build some FPGA logic that accelerated some parts of the game and get speedups from it. One advantage of an FPGA circuit is that at least you might not suffer penalties in places a normal CPU would with branch mispredictions, but it depends on the circuit design. Long, complex circuits are going to have terrible clock rates.
Actually, I'd really like to see just how much of DF's time is spent waiting on RAM. I haven't used a modern profiler in ages so I don't know if you can even get that information readily